The present invention relates to a semiconductor memory suited for, for example, a mobile terminal which operates by a battery. More specifically, the present invention relates to a semiconductor memory, such as an SRAM (Static Random Access Memory), which realizes high-rate operation at low power supply voltage.
As a technique related to this field, there has been known hitherto one described in the following document:
Shibata and Morimura, xe2x80x9c0.25-xcexcm SRAM Micro-Cell operating at 1V for Mobile Terminalxe2x80x9d, pp. 1-8, Shingakugiho, ICD97-52 (1997-6), Journal of IEICE (Institute of Electronics, Information and Communication Engineers).
An SRAM is widely used as a cache memory for an ASIC (Application Specific IC) or the like which is used in a mobile terminal or the like. Since the mobile terminal or the like employs a battery as a power supply, low power supply voltage and low power consumption are required for the mobile terminal or the like. If power supply voltage is decreased, the operating rates of MOS transistors which constitute the SRAM decrease. In turn, when the threshold voltages of the MOS transistors are decreased to accelerate the respective operating rates, in a standby state, leak current caused by sub-threshold current increases, thereby disadvantageously increasing power consumption.
To solve these disadvantages, there is proposed an MTCMOS (Multi-Threshold CMOS) based on a CMOS (complementary MOS transistor) LSI technique, which can operate at low power supply voltage (e.g., 1V) when being active and which can prevent an increase in power consumption due to leak current in a standby state.
FIGS. 6A and 6B show a conventional SRAM which utilizes the MTCMOS technique described in the above-cited document. FIG. 6A is a schematic block diagram showing the entire SRAM, and FIG. 6B is a circuit diagram showing the configuration of a memory cell and that of a peripheral circuit thereof.
As shown in FIG. 6A, this SRAM includes a memory cell array 10 consisting of high threshold voltage MOS transistors, and a peripheral circuit 20 consisting of low threshold voltage MOS transistors.
The memory cell array 10 is comprised of a plurality of word lines WLi and a plurality of bit line pairs BLj, /BLj (where xe2x80x9c/xe2x80x9d means inversion or low active) arranged to be orthogonal to the respective word lines WLi. Memory cells 11ij for data storage are connected to the intersections between the word lines and the bit line pairs, respectively.
The peripheral circuit 20 includes an address decoder 21 and an input/output circuit 22.
The address decoder 21 is a circuit which decodes a row address in an address signal AD applied from the outside of the SRAM, and selects a corresponding word line WLi in the memory cell array 10. The input/output circuit 22 is a circuit which decodes a column address in the address signal AD to output a column select signal/Yj, and which reads and writes data DA from and to the memory cells 11ij connected to the bit line pair BLj, /BLj selected by this column select signal/Yj in accordance with a read control signal/RE and a write control signal/WE, respectively.
The peripheral circuit 20 is connected to the power supply voltage VDD of a battery through a switch 23 consisting of a high threshold voltage MOS transistor. In a standby state, the switch 23 is controlled to be turned off using a sleep signal SL to thereby suppress the consumption of the battery caused by sub-threshold leak current. On the other hand, the memory cell array 10 is constantly turned on since the memory cell array 10 cannot be disconnected from the power supply during a standby state so as to hold the storage contents of the memory cells. Due to this, the MTCMOS technique is applied to the memory cell array 10 in order to suppress the sub-threshold leak current and to accelerate operation rate.
As shown in FIG. 6B, each memory cell 11ij in this memory cell array 10 includes a flip-flop FF consisting of high threshold voltage inverters L1 and L2 which hold data on nodes N1 and N2. A high threshold voltage N channel MOS transistor Q1 driven by the potential of the word line WLi connects the bit line BLj with positive phase to the node N1. A high threshold voltage N channel MOS transistor Q2 driven by the potential of the same word line WLi connects the bit line /BLj with opposite phase to the node N2.
Further, the memory cell 11ij includes an acceleration circuit AC which encourages discharging the bit line pair BLj, /BLj and thereby accelerates read operation. The acceleration circuit AC consists of low threshold voltage N channel MOS transistors Q3 to Q6. The transistors Q3 and Q4 are connected to the bit lines BLj and /BLj, respectively and driven by the potential of the word line WLi. The transistors Q3 and Q5 are connected in series and the transistors Q4 and Q6 are connected in series. One end of the transistors Q5 and Q6 are connected to each virtual ground line VGj arranged in parallel to the bit lines BLj. The transistors Q5 and Q6 are driven by the potentials of the nodes N1 and N2, respectively.
One end of the virtual ground line VGj is connected to a ground voltage GND through a high threshold voltage N channel MOS transistor 31j. The transistor 31j is controlled to be turned on and off by the output signal of a NOR circuit 32j which NORs the read control signal/RE and the column select signal/Yj.
The operation of the memory cell 11ij shown in FIG. 6B will next be described.
During data write, when the word line WLi is selected to be set at xe2x80x9cHxe2x80x9d level, the transistors Q1 to Q4 are turned on and the data of the bit line data pair BLj, /BLj is held in the flip-flop FF. At this moment, the read control signal/RE is inactive and set at xe2x80x9cHxe2x80x9d level. Therefore, the output signal of the NOR circuit 32j is at xe2x80x9cLxe2x80x9d level and the transistor 31j is turned off. Accordingly, the virtual ground line VGj turns into a floating state and the transistors Q3 and Q4 in the acceleration circuit AC do not influence data write operation.
During data read, when the read control signal/RE is activated to be set at xe2x80x9cLxe2x80x9d level and the column select signal/Yj is selected to be set at xe2x80x9cLxe2x80x9d level, the level of the output signal of the NOR circuit 32j becomes xe2x80x9cHxe2x80x9d level. As a result, the transistor 31j is turned on and the virtual ground line VGj is connected to the ground voltage GND. If the word line WLi is then selected to be set at xe2x80x9cHxe2x80x9d level, the transistors Q1 to Q4 are turned on. At this moment, one of the nodes N1 and N2 is at xe2x80x9cHxe2x80x9d level, so that one of the transistors Q5 and Q6 is turned on.
For example, when the node N1 is at xe2x80x9cHxe2x80x9d level and the node N2 is at xe2x80x9cLxe2x80x9d level, the transistor Q5 is turned off and the transistor Q6 is turned on. As a result, not only the inverters L1 and L2 drive the bit line pair BLj, /BLj but also the low threshold voltage transistors Q3 to Q6 having high current driving abilities drive the bit line pair BLj, /BLj. Thus, read operation can be accelerated. That is, when the xe2x80x9cHxe2x80x9d level of the node N1 and the xe2x80x9cLxe2x80x9d level of the node N2 are to be read, the transistor Q6 is turned on. Due to this, the potential of the bit line /BLj is decreased to the ground voltage GND through the transistors Q4, Q6 and 31j, accelerating the read operation.
Further, in a standby state, the high threshold voltage transistor 31j is turned off by the output signal of the NOR circuit 32j and the leak current caused by the sub-threshold currents of the low threshold voltage transistors Q3 to Q6 is shut off, so that low power consumption can be realized.
The conventional memory cell, however, has the following disadvantages.
During data read, the transistor 31j is turned on, the virtual ground line VGj is connected to the ground voltage GND, charge from the acceleration circuit AC is discharged to the ground voltage GND through this transistor 31j and the read operation is thereby accelerated.
In write operation performed after this read operation, the transistor 31j is turned off and the virtual ground line VGj turns into a floating state. At this moment, the potential of the virtual ground line VGj is close to the ground voltage GND. It is assumed herein, for example, that while the node N1 is at xe2x80x9cHxe2x80x9d level and the node N2 is at xe2x80x9cLxe2x80x9d level, inverted data is written to the nodes N1 and N2 (i.e., xe2x80x9cLxe2x80x9d level is written to the node N1 and xe2x80x9cHxe2x80x9d level is written to the node N2). In this case, when the level of the word line WLi rises to xe2x80x9cHxe2x80x9d level, the low threshold voltage transistors Q3 and Q4 are first turned on as compared with the high threshold voltage transistors Q1 and Q2 and then the transistors Q1 and Q2 are turned on late.
When the transistors Q3 and Q4 are turned on, the transistor Q1 is still turned off to thereby set the node N1 at xe2x80x9cHxe2x80x9d level and the transistor Q6 is, therefore, turned on. Due to this, the potential of the bit line /BLj is decreased to be equal to that of the virtual ground line VGj in a floating state which potential is close to the ground voltage GND, through the transistors Q4 and Q6. As a result, when the transistors Q1 and Q2 are turned on later and the xe2x80x9cHxe2x80x9d level of the bit line /BLj is to be written to the node N2, it is disadvantageously difficult to write the data to the bit line /BLj and the operation rate for writing the inverted data is disadvantageously decreased.
The present invention has been made to solve the disadvantages of the conventional art. It is, therefore, an object of the present invention to provide a semiconductor memory which can prevent write operation rate from being decreasing and which can operate at low power supply voltage with low power consumption.
To attain this object, a first invention of the present invention provides a semiconductor memory comprising: a bit line pair consisting of a first bit line and a second bit line complementary to each other; a pseudo power supply line provided to correspond to the bit line pair; a word line arranged to cross the bit line pair; a data holding circuit provided at an intersection between the bit line pair and the word line, and having a first node and a second node holding data complementary to each other; a high threshold voltage first transistor connected between the first bit line and the first node, and driven by a potential of the word line; a high threshold voltage second transistor connected between the second bit line and the second node, and driven by the potential of the word line; a low threshold voltage third transistor connected between the first bit line and a third node, and driven by the potential of the word line; a low threshold voltage fourth transistor connected between the second bit line and a fourth node, and driven by the potential of the word line; a low threshold voltage fifth transistor connected between the third node and the pseudo power supply line, and driven by the data on the second node; a low threshold voltage sixth transistor connected between the fourth node and the pseudo power supply line, and driven by the data on the first node; a first switch circuit connected between the pseudo power supply line and a ground voltage, and turned on when the data is read from the data holding circuit and turned off otherwise; and a second switch circuit connected between the pseudo power supply line and a power supply voltage, and turned on when the data is written to the data holding circuit and turned off otherwise.